VHDL: What is correct way to model open collector output for FPGA?

Published: 14/06/2019
VHDL: What is correct way to model open collector output for FPGA?
Source: ELECTRONICS.STACKEXCHANGE.COM

I2C uses open collector outputs. FPGAs do not have such outputs. They do have tri state buffers though. How should open collector output be defined in a VHDL for an FPGA? How should open collector output be pulled high in testbench? i.e how model the pull up resistor e.g on SDA line that connects master to slave, in a testbench?

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